Detecting end of SPI transaction (/SS1 or /SS2 going high) on MCF51CN128

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Detecting end of SPI transaction (/SS1 or /SS2 going high) on MCF51CN128

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armistej
Contributor III

With the MCF51CN128 in SPI master mode with SPI chip selects being generated automatically (MODFEN = 1, SSOE = 1), is there a way of synchronizing the software with the instant the SPI chip select (/SS1 or /SS2) goes high (i.e. once the last SPI write has been completed)

 

Reading the SPI status register SPxSR only allows me to see the SPTEF bit which indicates the transmit buffer is empty, not when the bits that were put into the SPxD data register have actually passed out the shift register via MOSIx

 

I think the only way I might be able to do would require me to be able to read the actual pin state.  Is it possible to configure the GPIOs so that even if SS1 or =S2 pin is configured by the pin mux controls (via PTxPF1 and PTxPF2 registers), then I'm still able to read the PTxD register and see the state of SS1 or SS2 pins as they change ?

 

Reading the Reference Manual I'm not certain if it's possible or not.

 

TIA,

Jason

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kef
Specialist I
  • Reading the SPI status register SPxSR only allows me to see the SPTEF bit which indicates the transmit buffer is empty, not when the bits that were put into the SPxD data register have actually passed out the shift register via MOSIx

 

You may use SPRF flag as a indicator of the end of transfer. Since shifting bits in happens simultaneously with shifting bits out, SPRF is set exactly when byte transfer (in and out) is complete.

 

char spitransfer(char c)

{

   // read SPIS as the first step of SPTEF flag clear sequence

   while( !(SPIS & SPIS_SPTEF_MASK) )

   {

   }

 

   // clear SPTEF writing data to to TX buffer. Send c

   SPID = c;

 

   // wait until transfer is complete

   while( !(SPIS & SPIS_SPRF_MASK) )

   {

   }

 

   // return received data and clear SPRF

   return SPID;

}

 

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