Watchdog in MQX 3.5.1

[elel]

Hi Everybody.

I'm trying to enable the watchdog timer in my software, I've decided to use the core watchdog.

I've setted at 1 the define MQX_USE_SW_WATCHDOGS, and I've installed the watchdog isr with this two function:

  _int_install_isr(MCF5225_INT_SWT,(void (_CODE_PTR_)(pointer))Core_WatchDog_Expire_Handle, NULL);
  _mcf5225_int_init(MCF5225_INT_SWT, BSP_WATCHDOG_INTERRUPT+1, BSP_WATCHDOG_INTERRUPT, TRUE);
 
And than I've create the watchdog isr routine that is this function:

void Core_WatchDog_Expire_Handle(pointer)
{
    VMCF5225_STRUCT_PTR reg_ptr = _PSP_GET_IPSBAR();
    reg_ptr->CCM.RCR = 0x80;
}

And the watchdog it's working well.

Now my question is: why the MQX manage the watchdog refresh into the PIT0 isr routine?

I think it's better to refresh the watchdog timer into the main of the software, because if the main is blocked the watchdog timer reaches the underflow and the interrupt is generated and if the interrupt is blocked the main is not running(because the interrupt as an higher priority) and the watchdog is reached too.
Instead if the watchdog timer is refreshed into the PIT0 isr and if the main is blocked but the interrupt it's running the watchdog will never reached.

Stefano

[DavidS]

Hi Stefano,

I think the subject of watchdog implementation is equally complex as benchmarking!

There are multiple levels of watchdog capability with ColdFire and FSLMQX.  To date I have not found any one to be the best solution but rather a combination of watchdog's being implemented to help make the design more robust.

ColdFire:

The core watchdog must be serviced regularly and the most regular event that occurs is the BSP_TIMER incrementing the system tick.  When the core watchdog timers times out (your code is good example) an ISR routine can be used to save off system information (i.e.. log stuff) and then issue a software rest (as your code does).  FSLMQX does implement this but by default does not enable/active it as it prevents debugging capability as core watchdog does not stop decrementing when processor is HALTed.

There is also a backup watchdog timer that once it times out the system does a hard rest.  This watchdog isn't directly supported other then having its registers defined as well as structure to access/enable it.  It is defined in the mcf5225.h header of the PSP...look for MCF5225_WATCHDOG_STRUCT.

FSLMQX:

Lastly MQX has a capability to implement task watchdog timers (reference ~mqx/examples/watchdog) that will ensure task do not fail and if they do then an ISR routine is called and decision as what to do can be done (ex: reset device, kill task and try reset, log stuff, etc.).  The example simply logs to terminal which task failed.  I enhanced the code to work with multiple tasks as originally it was working with only one. 

So your point about where to place the watchdog resetting code is valid and I think more of a system engineering design than one way fits all designs.

Best Regards,

David

[ARQuattr]

---

DavidS wrote: 

... FSLMQX does implement this but by default does not enable/active it ....

---

Hi David,

  I'm interested to implement the core watchdog - is it possible to enable it without adding the ISR?  Do I understand correctly, that if I...

#define BSP_WATCHDOG_INITIALIZATION BSP_WATCHDOG_RESET

...it will simply reset on its own without me needing to add the ISR?

  I'm also a little confused about the terminology.  The core watchdog is often refered to as the SW watchdog, but this is not a software timer right?  This is the timer on the processor hardware? 

  Also is the backup timer an independant hardware timer, or is it using the same core watchdog timer?  I'm not clear how I would use the MCF5225_WATCHDOG_STRUCT, or if I even need it (what it provides me).

Thanks,

Angelo

[DavidS]

Hi Angelo,

The core watchdog and the backup watchdog timers are separate hardware modules integrated on-chip.

The core watchdog does require having an ISR routine.  The intent of the ISR is to allow user code to evaluate and/or log current state of the system and then issue a software reset to get system back and running normally.

The backup watchdog timer does not use ISR.  When it times out it will reset the MCU.

The MCF5225_WATCHDOG_STRUCT allow you direct access to the register to configure the backup watchdog module.

Regards,

David

[elel]

Hi David

Thanks for your answer.

So, if I've understand correctly, I let the MQX handle the core watchdog(the only thing I'll do is to install an isr to manage the watchdog event), and I can work on the backup watchdog timer and on the task watchdog timers.

It's right?

Another question: I've read the refernce manuale of the 52259, but I've not understand completely  the difference between the "core watchdog timer" and the "backup watchdog timer", can you explain me wich is?

Stefano

[DavidS]

Hi Stefan,

Sorry for delay...decided to see if a summer cold would be fun or not.  I decided it is not fun!

I agree with your statement on usage.

The difference between core and backup watch dog is to fold.  The core watchdog cannot be stopped when debugging (i.e. hitting breakpoints and singlestepping) and it must execute an ISR (a way to allow some cleanup and/or logging before issueing  a software rest).

The backup watchdog can be used when debugging and will cause an immediate hardware reset.

Regards,

David

[elel]

Hi David.

Thanks  for the answers, now I'll try to develop the managing of the backup watchdog.

Stefano