Hello,
I am doing bit I/O operations that need to be interrupt and thread safe.
Compiler was set with optimization off and small code size, but for the most part the
code didn't change at all or only moved the order of some instructions around when set
for level 4 optimization and fast code.
Source code:
PTED = (unsigned char)(PTED ^ 4); // 170 nS
Generated Assembly:
0x000001C6 0x71B88008 mvz.b 0xffff8008,d0
0x000001CA 0x08400002 bchg #2,d0
0x000001CE 0x11C08008 move.b d0,0xffff8008
//
// The above bit operation is not thread / interrupt safe
//
//
Source Code:
PTED_PTED2 = ~PTED_PTED2;
Generated Assembly:
0x000001F6 0x70FB moveq #-5,d0
0x000001F8 0x14388008 move.b 0xffff8008,d2
0x000001FC 0xC480 and.l d0,d2
0x000001FE 0x73B88008 mvz.b 0xffff8008,d1
0x00000202 0x701D moveq #29,d0
0x00000204 0xE1A9 lsl.l d0,d1
0x00000206 0x701F moveq #31,d0
0x00000208 0xE0A9 lsr.l d0,d1
0x0000020A 0x4681 not.l d1
0x0000020C 0xA340 mov3q #1,d0
0x0000020E 0xC280 and.l d0,d1
0x00000210 0x7181 mvz.b d1,d0
0x00000212 0xE588 lsl.l #2,d0
0x00000214 0x8480 or.l d0,d2
0x00000216 0x11C28008 move.b d2,0xffff8008
//
// The above is not thread safe and there is a lot of extra operations going on - why two initial reads from the
// port and why all the bit shifting, left then right?
//
// As a side note I have tried manipulating a union / structure of bit fields and it generates very similar code. This
// is going to be big performance hit in the code I will be porting over for this target processor as the application
// has extensive bit definitions in structures.
//
// I have coded the bit change in assembly:
asm{
moveq #2, d0
bchg d0, _PTED // 170 nS
}
//
// Thread / interrupt safe
// Any way to force the compiler to handle these bit operations as I have done in assembly?
A second side question, is there a way to easily turn off interrupts for the MCF51JM128 so I can make these
operations safe.
Thanks for your help.
Will
