I got confused in using the external clock TCLK. It seems this pin is shared with the /RESET function and if POR is also used, a capacitor is tied here. How do I wire this pin for a counter with a reset design?
Hello and welcome to the fora, marcoh.
The pin in question powers up with the general purpose I/O function.
It will not act as a reset pin unless explicitly enabled in the SOPT1 register. Note that this is a "write once" register so you can never disable the pin if you enable it (without a POR).
So in summary it will never act as a reset pin unless you tell it to.
The low voltage detect feature and the POR sequence still operate regardless of the enabling of the reset pin.
You should still make a write to the SOPT1 register even if you are happy with its default state to allow its write once mechanism to protect against subsequent writes.
I like the S08SHx chips. As you've discovered, the architects have tried to offer a range of functionality but it can make you choose some feature over another. Some would say look at another chip but the S08SHx for some reason may be your only choice.
As has been mentioned recently in this forum, you could alternatively use the input capture timer channels and count edge interrupts. This would leave the pin free to use as reset. But it means for the timer input capture pin an interrupt occurs on every edge(up&down) or second edge(up or down).
The risk is if the frequency of your clocks/frequently transiting input is very high, maybe the interrupts can't be serviced fast enough or it hogs processing time for other routines.
If this was possible for your project, you could use the reset pin and still count edges of some signal.
Another option though unattractive, is to use some sort of supervisory circuit/IC with a reset input to cycle power to the uC. That would free the pin for TCLK and still have a RESET. A bit messy though.
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