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MCF5329 MSCR_FLEXBUS and MSCR_SDRAM Registers, how do they work in SDR mode?

Question asked by TomE on Jun 7, 2010
Latest reply on Jul 6, 2010 by TomE

The MCF5329 can have its pins set up with different drive strengths.


Can anyone help me understand what the MSCR_SDRAM and MSCR_FLEXBUS registers "mean" when using 3.3V SDR? The Reference Manual only seems to document DDR mode.

This is well documented for all pins EXCEPT the Flexbus and SDRAM controller ones.


Typical non-SDRAM/FlexBus pins can be set up as:


  • 00 10pF
  • 01 20pF
  • 10 30pF
  • 11 50pF

The MSCR_FLEXBUS and MSCR_SDRAM pins are documented as:


  • 00 Half strength 1.8V Mobile DDR.
  • 01 Open drain.
  • 10 Full strength 1.8V Mobile DDR.
  • 11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

That implies the only options for 3.3V SDR chips is the last one.


But I really need 3.3V SDR with a low drive strength like the MCF5235 supported in the programming of its DSCR_EIM register.

So what does it mean to set the register to 00, 01 and 10 when the:


  • SVdd pins are connected to 3.3v (and not 1.8 or 2.5),
  • The Flexbus is configured for non-DDR, and
  • The SDRAM controller is configured for SDR?


If I change the values in the above registers while monitoring what is actually happening on the data bus I find that "00" does drive with a lower strength than when set for "11", so it is doing SOMETHING, but I don't know what.


The MCF5329 manual doesn't give any more help on this.


The MCF53277 manual (and MCF5208 ones) are 99% cut-and-paste from each other, except that the MCF53277 additionally states:

19.6.1    SDR SDRAM Initialization Sequence
   3. Configure the slew rate for the SDRAM external pins in the pin multiplexing

      and control module’s MSCR_SDRAM register if needed.

So that one implies that MSCR_SDRAM can be used in SDR mode. But the documentation of that register in that manual is identical to the one in the MCF5329, and doesn't detail what the settings mean for SDR. That manual forgets to mention changing MSCR_FLEXBUS when changing MSCR_SDRAM - that's an accidental omission.


All manuals have bad cut-and-paste bugs for MSCR_SDRAM too. They all state "SD_CLK mode select control. These bit fields control the strength of the FlexBus lower data pins." which is the description from the PREVIOUS table.