Background:
Questions:
i. Programming speed
ii. What if the LRAE flash area accidentally gets erased?
Thanks,
Toby Landes
Valquest Systems, Inc.
1. Of course S12A512 will do easily all tasks HC11 is able to do. S12 top bus clock is ~25MHz, and best HC11 IIRC was only 5MHz. S12 code density is better than HC11 code density, so I'm not sure you need 512kB for code space. If you plan to use tens and hundreds kB of data in flash, then I suggest you using something from available S12X families. S12X would greatly improve the speed and lower the overhead of paged data memory accesses (in flash). On S12 paged data memory accesses are way more slower in case your application requires a lot of const data in flash. 16-30kB of data in flash is almost ok, no problem until nonpaged code (ISR's and some runtime routines) plus data fits limited nonpaged flash. But above that, when you will be forced to move data to paged flash, there will be a lot of overhead sharing single PPAGE register for both, code paging and data paging. S12X is better in this aspect, you have global memory addressing and can read/write all available memory without the need to switch PPAGE register.
2. Single chip design is more robust, less noisy etc. Of course you can run S12 or S12X in single chip mode..
3.1. There's no JTAG on S12(X), but there's single pin BDM interface, which allows to program flash memory and to debug. You need BDM adapter for this. I think most popular is P&E (www.pemicro.com) USB Multilink (USB-ML-12).
3.2 LRAE was to help hobbysts avoid BDM interface expenses, so that they could use RS232 to flash chips. Motorolla/Freescale was going to flash LRAE to every chip at factory programming, but this idea was abandoned many years ago. Additional production operation would mean more costs and more expensive parts. So you have only BDM option.
XGATE is interrupts coprocessor. It's an additional RISC CPU, that can service interrupts and when interrupt servicing is done, XGATE can let main CPU continue interrupt servicing or trigger different CPU interrupt. It can be used for many things. For example SCI ISR handler could collect higher level protocol packet data, validate packet checksum and disturb CPU only when valid packet is received etc. You may check application notes.
You may also look at more fresh (than S12XA) S12XE family. It is faster, contins 12-bits ADC instead of 10-bits ADC available on S12XA etc.