Warning C12056

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Warning C12056

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WadeH
Contributor III

I am using CW 5.9.0 with a 9S12C32. After some recent edits, I am now getting the compiler message:

 _      Warning: C12056: SP debug info incorrect because of optimization or inline assembler


No inline assembly is involved, except the macro EnableInterrupt, and no amount of disabling optimizations makes this message go away.

I can't blame any code misbehavior on this (wish I could) but I would like to know exactly what it means. The help-file explanation is a real eye-glazer

 

Wade H

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CompilerGuru
NXP Employee
NXP Employee

It did you try to disable the common code optimization with -onf?

 

What it means is that the stackpointer has different values in a single location in a function depending on how the code gets to this location. With the common code optimization (to disable use -onf) this may happen in legal code.

Conceptually this happens for a setup like this:

 

void fun(void) {

  ....

  CC;

  ...

  PSHA

  ...

  CC;

  ...

  PULA

  ...

  RTS

}

 

CC is a list of identical assembly instructions.

 

In this setup, the compiler moves the common code part CC to a new location and replaces the two old locations with JSR to the shared place for CC. As the two JSR's are located at different SP levels, the compiler issues the warning for the new location of the CC code.

 

optimized function:

 

void fun(void) {

  ....

  JSR CC_Label

  ...

  PSHA

  ...

  JSR CC_Label

  ...

  PULA

  ...

  RTS

 

CC_Label:

  CC

  RTS

}

 

Daniel

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CompilerGuru
NXP Employee
NXP Employee

It did you try to disable the common code optimization with -onf?

 

What it means is that the stackpointer has different values in a single location in a function depending on how the code gets to this location. With the common code optimization (to disable use -onf) this may happen in legal code.

Conceptually this happens for a setup like this:

 

void fun(void) {

  ....

  CC;

  ...

  PSHA

  ...

  CC;

  ...

  PULA

  ...

  RTS

}

 

CC is a list of identical assembly instructions.

 

In this setup, the compiler moves the common code part CC to a new location and replaces the two old locations with JSR to the shared place for CC. As the two JSR's are located at different SP levels, the compiler issues the warning for the new location of the CC code.

 

optimized function:

 

void fun(void) {

  ....

  JSR CC_Label

  ...

  PSHA

  ...

  JSR CC_Label

  ...

  PULA

  ...

  RTS

 

CC_Label:

  CC

  RTS

}

 

Daniel

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