Marilena Nardelli

ICS protection against loss of lock an loss of clock

Discussion created by Marilena Nardelli on May 18, 2010
Latest reply on May 23, 2010 by bigmac


I'm currently using a QE8 microcontroller in my application. The ICS module is designed for lower power operation and has no features that allow monitoring of loss of lock or loss of clock. I read  AN3499, on paragraph 2.1.7, in the event of loss of lock, the ICS attempts to regain FLL on its own. I have doubt on this sentence, it means that the microcontroller change it mode of operation and come in default mode, FEI, if a loss of lock occur?


The ICS module contains an indipendent clock source for the COP watchdog timer that can rest the MCU if the CPU and bus clocks are corrupted. I suppose to enable the COP watchdog and use for it the indipendent clock source (1KHz clock), if a loss of clock occur, betwen this event and the COP reset the MCU, the bus frequency falls to 0Hz?


Thanks in advance.