Andreas Oedling

Error in MCF52223RM ?!

Discussion created by Andreas Oedling on May 15, 2010
Latest reply on May 15, 2010 by Stan Chernikov


Hi! On page 25-25 in the MCF52223RM, it says


The ADC consists of a cyclic, algorithmic architecture using two recursive sub-ranging sections (RSD#1

and RSD#2), shown in

clock, resulting in an overall conversion rate of two bits per clock cycle. Each sub-ranging section is

designed to run at a maximum clock speed of 5.0 MHz. Thus a complete 12-bit conversion takes 6 ADC

clocks (1.2ms), not including sample or post processing time."



I'm guessing that it should be µs, instead of ms :smileywink:


just in case you want to change it!

I found no other way of contacting freescale, save starting a support errand...