I’m using the HCS12XEP100 and need to set the FCLKDIV register. The target frequency is 1MHz (many other flashes require 200K).

So the divisor should be pretty simple then, basically it should be whatever the OSC clock is, in MHz.

There is a table in the XEP reference manual (MC9S12XEP100RMV1.pdf Rev. 1.21 04/2010 page 1151) which shows recommended values for FCLKDIV for OSC values. But the values in the table don’t seem to be simple divisors.

For example, at an OSC of 10MHz, the recommended value is 0x09, where I might expect a value of 10. I can imagine a (maybe undocumented or did I miss something?) additional +1 in there to get the expected 10.

But the difference is greater at higher OSC frequencies. At an OSC of say 48MHz, the table shows a value of 0x2D, which is 45 where I might expect 48. My imaginary +1 doesn’t work in this case so it seems there is some other factor.

Could you confirm please that the divisor really is a simple divisor with no additional factors, or how the table in the manual was derived? I’m not sure at the moment what FCLKDIV value to use and don’t want to damage the flash. Many thanks.

Dear StevieG,

At the bottom of the table there are two notes:

1. FDIV shown generates an FCLK frequency of >0.8 MHz

2. FDIV shown generates an FCLK frequency of 1.05 MHz

that apply to the fmin and fmax values of the table respectively.

From this it would appear that the flash will tolerate a frequency from 800kHz to 1.05MHz. Using these numbers you can arrive at the fmin and fmax values in the table assuming a formula of

Fflash = Fclk / (fclkdiv+1) with the FURTHER action of of moving the fmin value up so that it does not overlap the next lower fmax value.

A bit arbitrary I think. Use of a geometric mean as the boundary when they overlap would be more appealing.

Bye