I have a successful design that uses RCON asserted and *RSTOUT gated configuration which works perfectly.
Due to space limitations I am trying to remove the gated configuration devices (resistor, capacitor and '573 TTL device) since we conform to the "default" reset configuration.
With RCON pulled high the 5208 start as expected and executes from our 16 bit flash but runs at the lower speed (as expected from the default reset configuration with RCON high).
I then try to reconfigure the Clock Module to achieve our required 166/83Mhz (core/bus) speed but cannot achieve this with the setting of the PORD and PFDR registers (see following code), we have a 16MHz crystal reference.
//Enter Limp mode, change clock, back into normal mode and wait for a PLL lock.
Changing the PODR and PFDR registers do have an effect on the operation be not what we expect.
All other operation seems perfect and we have used this device with "asserted RCON+gated configuration" and it works correctly.