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PLL falls out of lock   9s12xhz

Question asked by Darrell Martin on Apr 9, 2010
Latest reply on Apr 16, 2010 by Darrell Martin

I am running a 9s12xhz512. It runns a short piece of startup code then sets the PLL to 40mhz bus speed (8mhz xtal) and sets the system clock to that. I then do a ram and rom test and everything is fine until I enable the RTI (and only the RTI). 2.1us after the RTI occurs the PLL falls out of lock and then 104us later it re-aquires lock but can only hold it for ~2us before falling out again. This falling in and out of lock continues forever even if I  disable RTI after the first failure.


I have verified that if I never enable the RTI it will hold lock forever. All that is in the RTI routine is clearing the RTI flag and toggling a pin on portb.


I am collecting this data with a scope using port pin toggles in the RTI and PLL_lock_interrupts.


I get the same results with or without the BDM connected.


We have checked our PLL component values and belive them to be correct. I have 5 other products using different circuit boards and different code and none of them are showing this issue. I can find no difference between them in either cicuitry, component values, or code related to the clocks and PLL.


I am really stumped here... any great ideas?