Hello,
i want to read the ADRSLTn-Registers with a DMA-Request. I used an DMA-Timer which request periodically a DMA-Transfer. The problem is that the RDY-Bits in the ADSTAT no be cleared. So i get always the same result. The ADC runs in loop-Mode with fastest speed, so an complete measurement is much faster then the DMA-Timer. Can everyone help me? Thanks.
I implemented ADC data collection with DMA. The purpose was to reduce noise by averaging. I set up a buffer to collect 128 samples of each channel, a DMA channel and a DMA timer. The DMA timer was configured to trigger at the rate of the ADC or slower. Works great. I didn't encounter any issues with the RDY bits. One funny thing I noticed: for some reason the ADRSLTn registers' addresses are not aligned to a 16-byte boundary, they are off by 2 bytes. This isn't good for DMA since it likes aligned addresses, so some buffer memory is wasted.
Hi Scifi, I think I do it the same way, only the buffer is smaller. I get only a correct value from the ADC when I read the ADC normally between the DMA-Transfers. My intention was also to reduce noise by averaging. Can you post me some parts of your code or correct my code? Many thanks before...
MCF_DMA_DMAREQC = MCF_DMA_DMAREQC_DMAC0(4);
MCF_DMA0_SAR = MCF_DMA_SAR_SAR(0x40190012);
MCF_DMA0_DAR = MCF_DMA_DAR_DAR((uint_32)&dma_adc_array[0]);
MCF_DMA0_BCR = MCF_DMA_BCR_BCR(16);
MCF_DMA0_DCR = MCF_DMA_DCR_START |
MCF_DMA_DCR_DSIZE_BYTE |
MCF_DMA_DCR_DINC |
MCF_DMA_DCR_SSIZE_BYTE |
MCF_DMA_DCR_SINC |
MCF_DMA_DCR_EEXT;
MCF_DTIM0_DTXMR = MCF_DTIM_DTXMR_DMAEN;
MCF_DTIM0_DTER = MCF_DTIM_DTER_REF;
MCF_DTIM0_DTRR = 200;
MCF_DTIM0_DTMR = MCF_DTIM_DTMR_RST |
MCF_DTIM_DTMR_CLK_DIV1 |
MCF_DTIM_DTMR_FRR |
MCF_DTIM_DTMR_ORRI |
MCF_DTIM_DTMR_PS(15);
The comments in my code are not in English, so I stripped them before posting:
#include "adc.h"#include "config.h"#include "mcf52233regs.h"#include "irq.h"#define ADC_CTRL1 MCF_REG16(0x190000)#define ADC_CTRL2 MCF_REG16(0x190002)#define ADC_POWER MCF_REG16(0x190052)#define ADC_ADZCSTAT MCF_REG16(0x190010)#define ADC_RSLT7 MCF_REG16(0x190020)#define CTRL_START (1 << 13)#define CTRL_STOP (1 << 14)#define CTRL_SIMULT (1 << 5)#define POWER_PD0 (1 << 0)#define POWER_PD1 (1 << 1)#define POWER_PD2 (1 << 2)#define POWER_PSTS0 (1 << 10)#define POWER_PSTS1 (1 << 11)#define DMA_DMAREQC MCF_REG32(0x14)#define DMA_SAR0 MCF_REG32(0x100)#define DMA_DAR0 MCF_REG32(0x104)#define DMA_BCR0 MCF_REG32(0x108)#define DMA_DCR0 MCF_REG32(0x10C)#define DMAREQC_DTIM0 4#define DCR_INT (1u << 31)#define DCR_EEXT (1 << 30)#define DCR_CS (1 << 29)#define DCR_AA (1 << 28)#define DCR_SINC (1 << 22)#define DCR_SSIZE_WORD (2 << 20)#define DCR_DINC (1 << 19)#define DCR_DSIZE_WORD (2 << 17)#define DCR_SMOD_16 (1 << 12)#define DCR_DMOD_2K (8 << 8)#define DCR_D_REQ (1 << 7)#define DSR_DONE (1 << 24)#define SCM_MPARK MCF_REG32(0x1C)#define SCM_MPR MCF_REG8(0x20)#define MPARK_BCM24BIT (1 << 24)#define DTIM_PERIOD 40#define DMA_INT_NUM 9#define DMA_INT_VECT 292#define ADC_NCHANNELS 8#define ADC_PORT_MASK 0x3F#define ADC_NSAMPLES 128#define DMA_NBYTES ((((1<<24) - 1) / sizeof(buffer)) * sizeof(buffer))#define ADC_MODE 3#define ADC_CLK_DIV 2#define DTIM_NUM 0#define DCR_DMOD DCR_DMOD_2K#pragma ghs section sbss=".adcbuf"static uint16_t buffer[ADC_NSAMPLES][ADC_NCHANNELS];#pragma ghs sectionIRQ_HANDLER_PREFIXvoidadc_dma0_handler(void){ DMA_BCR0 = DSR_DONE; DMA_BCR0 = DMA_NBYTES; DMA_DCR0 = DCR_INT | DCR_EEXT | DCR_CS | DCR_SINC | DCR_SSIZE_WORD | DCR_DINC | DCR_DSIZE_WORD | DCR_SMOD_16 | DCR_DMOD_2K | DCR_D_REQ;}#pragma intvect adc_dma0_handler DMA_INT_VECTstatic voidconfig_dma(uint8_t level, uint8_t prio){ SCM_MPR |= (1 << 2); SCM_MPARK |= MPARK_BCM24BIT; DMA_DMAREQC = DMAREQC_DTIM0; DMA_SAR0 = (uint32_t)&ADC_ADZCSTAT; DMA_DAR0 = (uint32_t)buffer; DMA_BCR0 = DMA_NBYTES; DMA_DCR0 = DCR_INT | DCR_EEXT | DCR_CS | DCR_SINC | DCR_SSIZE_WORD | DCR_DINC | DCR_DSIZE_WORD | DCR_SMOD_16 | DCR_DMOD_2K | DCR_D_REQ; irq_config(DMA_INT_NUM, level, prio, adc_dma0_handler); irq_unmask(DMA_INT_NUM); DTIM_DTXMR(DTIM_NUM) = DTXMR_DMAEN; DTIM_DTRR(DTIM_NUM) = DTIM_PERIOD; DTIM_DTMR(DTIM_NUM) = DTMR_ORRI | DTMR_FRR | DTMR_CLK_DIV1 | DTMR_RST;}voidadc_init(uint8_t level, uint8_t prio){ GPIO_PANPAR = ADC_PORT_MASK; ADC_CTRL1 = CTRL_STOP | ADC_MODE; ADC_CTRL2 = CTRL_STOP | CTRL_SIMULT | ADC_CLK_DIV; ADC_POWER &= ~(POWER_PD0 | POWER_PD1 | POWER_PD2); while ((ADC_POWER & (POWER_PSTS0 | POWER_PSTS1)) != 0) { } ADC_CTRL1 &= ~CTRL_STOP; ADC_CTRL1 |= CTRL_START; config_dma(level, prio);}uint16_tadc_read(uint8_t channel){ if (channel == 7) { return ADC_RSLT7; } else { int32_t sum = 0; uint8_t i; for (i = 0; i < ADC_NSAMPLES; i++) { sum += buffer[i][channel + 1]; } sum /= ADC_NSAMPLES; return (uint16_t)sum; }}