AnsweredAssumed Answered

M5225x Spurious Interrupts

Question asked by Mark Butcher on Feb 6, 2010
Latest reply on Feb 8, 2010 by Mark Butcher

Hi All

 

Does anyone have any words of wisdom concerning the following?

 

1) An M52259 is being used to transfer data between USB and UART0 [UART is 115k and the USB is in CDC class so is seen as a virtual COM port on the PC]. The transfer is bidirectional (at the same time) and during the test case text files are sent between two terminal emulators (several MBytes in size so that the test takes a bit of time).

 

This test runs reliably.

 

2) At the same time there is a web server running on the M52259 and this is tested in parallel by continuously and quickly refreshing a page with a fairly large image to that there are a high number of TCP transfers on each refresh.

 

When the two tests are run at the same time the board will fail at some point (hang).

 

3) The reason why it hangs is due to a spurious interrupt (the spurious interrupt routine hangs so that the cause can be looked into). It is found that the interrupt level, when the spurious interrupt occurs, is level 3.

 

It is also seen that usually, when the spurious interrupt occurs, there are three interrupts pending (UART0 Rx interrupt, UART0 Tx DMA interrupt and Ethernet Rx interrupt - sometimes also the USB-OTG interrupt, but not always). The two UART0 interrupts are interrupt level 3 (but different priorities - also no two interrupts in the system are configured with colliding level/priority). The Ethernet interrupt is level 6.

 

4) Just before the spurious interrupt takes place there is a small amount of data corruption in both directions (at least in one recording).

 

5) When the UART0 Tx operation is changed from DMA based to interrupt driven (interrupt for each transmitted byte rather than DMA based with a single interrupt after a block of bytes) the system runs reliably. It is then not possible to disturb the USB<->UART transmission test by a stress test on the Ethernet interface.

 

 

The question is thus, what could be the cause of the disturbance (resulting in a level 3 spurious interrupt - presumably from the UART0 DMA transmission completion) due to Ethernet activity? Why is this restricted to the UART Tx DMA, whereas in Tx interrupt driven mode there are many more interrupts taking place? What can cause a spurious interrupt (I have to admit to never having seen one before when working with the Coldfires)? Can it be something due to the fact that Ethernet and UART are working with DMA rather than the interrupt itself? Has anyone experienced such a problem and has any ideas as to what should be done?

 

Regards

 

Mark

Outcomes