AnsweredAssumed Answered

ACCERR randomly set on XD256, mask set 1M84E

Question asked by Steve Melnikoff on Jan 6, 2010
Latest reply on Jul 29, 2011 by kef

We wrote a bootloader for the XD256. It was initially tested on an XD256 mask set 0L15Y, and worked fine.


The same code was later programmed into an XD256 with mask set 1M84E, and failed at the start of every file download.


The problem appears to be that ACCERR is being set randomly at some point prior to any flash operations. When the first flash operation is triggered, ACCERR is checked, found to be set, and cleared. This should allow the operation to proceed, but it is not.


I've used the debugger to see what's going on, and discovered something else strange: if I single step through the code, then ACCERR remains clear after a reset. However, if I run the code - even if I set a breakpoint for the line immediately after the current one, and press Run - then the bit is set!


I've tried this with interrupts enabled and disabled during single-stepping. I've also tried the bootloader with flash protection and security on and off. Nothing seems to make any difference.


As I said, identical code worked perfectly on the other mask set, and I couldn't see anything obvious on the errata for the two masks, nor in the family data sheet.


So: any ideas?