In my first 9S12 design, I haven't paid enough attention to the PLL loop filter since I knew I was not going to use the PLL. On power-up of all 6 prototypes, I found SCM was setting and the BDM pod was reporting a bus frequency of 1.48 MHz instead of the 4 MHz I expected from the 8 MHz pierce oscillator with 8M2 resistor across the xtal and two C of 22p each to gnd.
Looking at the board, I saw I had put the PLL filter too far awy from the chip and obviously it was picking up noise in the lands.
So I cut the lands to the PLL filter, bypassed the Vdd PLL with a 100nF at the chip, and all seemed well. For a couple of months I have been successfully develping software using the 6 prototypes. I have got a clean 8MHz clock of 2V p-p from the xtal.
All of a sudden today, all six boards have gone back to a 1.48MHz bus speed! It`s like the laws of physics have changed overnight. I can`t think of anything that has changed.
Since there is little risk to having a cpu failure (it is a ham radio project) I would be happy if I could just disable the clock test circuitry and have it merrily using the 8MHz xtal. Can anybody tell me how to do this, since I can't find any way by reference to the data books.
Or any solution to my problem other than re-designing the board, since it is pro-bono I don't want to shoulder that expense.
Thanks for any help,
Nigel Johnson
