Roland Borrmann

9S08DZ32: How to handle writes to SRS for proper watchdog (COP) reset?

Discussion created by Roland Borrmann on Dec 3, 2009
Latest reply on Dec 5, 2009 by bigmac

Hello,

 

what is the proper way (after enabling the watchdog mechanism in the registers SOPT1 and SOPT2) to write to SRS in order to (periodically) reset the COP watchdog?

 

In the data sheet rev.4 for 9S008DZ60 family I read: "Writing a 0x55-0xAA sequence to this address clears the COP watchdog timer".

 

Does this mean the timer is reset in the moment the second byte is written to SRS?

Or does timer reset occur *each time* one of these bytes is written?

 

As far as I understand it right now it only matters that an endless sequence of 0x55/0xAA/0x55/0xAA....(as long as the time which elapses between the byte-writes does not exceed the COP timeout) has to be written to SRS. I went through many posts in this forum but I did not find an answer to my question above.

 

I also tried all this on a real system but all I get is endless COP resets no matter how I implement the writes to SRS. So I suspect that I have a faulty understanding of how SRS need to be written to.

 

 

Thanks for any help.

 

Regards

-Roland 

Outcomes