AnsweredAssumed Answered

PPC 8270: Running out of IMMR RAM (in order to run with ECC enabled)

Question asked by Karl Hahn on Dec 2, 2009
Latest reply on Dec 4, 2009 by Karl Hahn

I am copying a short program into IMMR RAM and trying to execute it there. It doesn't work. No opcodes are executed and the program counter runs backward (as if there were a "b  *-4" instruction in every location).


Is there a way to make this happen properly, or is running code out of IMMR RAM completely verboten?


The reason I am attempting such an unusual thing is this. I am trying to run with the ECC feature turned on using our development system under CodeWarrior. The program is running out of SDRAM, but this is the same chip select that the ECC affects. The program load is done with ECC disabled. Even if I enable it in the config file, the JTAG program load still does not set the syndrome bits correctly. So what happens is that as soon as I enable ECC, the code-space is exposed to incorrectly set syndrome bits, and the HW starts trying to "correct" my opcodes. Within a few instructions of enabling ECC, I get check-stopped for illegal op-code.


So what I'm trying to do is run a short program out of IMMR RAM (which is not affected by ECC) that will copy all of my code-space to itself, reading with ECC disabled and writing with ECC enabled. The intent is that this will set all the syndrome bits in the code-space correctly. But without the ability to do instruction fetches out of IMMR RAM, this plan is not very useful.


If anybody can think of a plan B to run out of SDRAM with ECC enabled, please let me know.