240MHz MCF5329 on our own board with 32-bit SDRAM and FLASH on the FlexBus. The LCD is in use, but disabled for these tests.
I'm testing memory copy and write speed and maxing at 80MB/s. I'd hope for higher with 80MHz 32-bit wide SDRAM.
The clocks are running at the right speed (240MHz/80MHz).
The Cache is on, in Writethrough mode (writeback is a lot slower) and the cache write queue is on (also makes a big difference). The Crossbar is set up to allow bursting. I've got interrupts and all DMA disabled during these tests. Code is running from SDRAM,but running it from SRAM only makes a tiny (1%) difference.
I can't find any information in the data sheet or user manual on what the expected SDRAM bandwidth should be. There are simple diagrams in the hardware manal, but they only give a RAS/CAS cycle and don't detail what back to back cycles with the SDRAM pages open should look like.
"AN3606 Understanding LCD Memory and Bus Bandwidth Requirements" gives the bandwidth as 128MB/s, without any derivation. This corresponds to 8 million four-word burst transfers per second, or 10 clocks at 80MHz. That seems excessive overhead, but it might be right.
I'm measuring 80MB/s for a sustained write to SDRAM (with the library memset), which is 16 clocks per burst - six clocks higher than that implied by AN3606.
Copying 192k blocks of data from SDRAM to SDRAM with a good library memcpy() gives about half that (as expected).
Turning the LCD DMA on at 11.5MB/s drops the CPU performance by 15%. So on that measure 100% is 11.5/15% or 77MB/s, matching the above figures.
At the moment it looks like the SDRAM timing might be suboptimal - I'm going to check that again.
Would the FLASH on the FlexBus be slowing the SDRAM down? The code isn't executing from there (all code is copied from FLASH to SDRAM and run from there).
Can anyone sugest anything else we might have missed?