Pete Smith

A to D interrupt issues

Discussion created by Pete Smith on Nov 3, 2009
Latest reply on Nov 3, 2009 by kef

Hey guys,


I am trying to get the A to D interrupts working with a simple program but am having some issues. I am using a mc9s12dg128b uP with Codewarriors Serial Monitor on a demoboard with a 8MHz clock. I have scaled my code down to its bear bones in an attempt to make the interrupts work. 

 

My code is as follows:

 



#include <hidef.h>      /* common defines and macros */
#include <mc9s12dg128.h>     /* derivative information */
#pragma LINK_INFO DERIVATIVE "mc9s12dg128b"



void AD0_Config()
  {
    ATD0CTL2 = 0xc2;
    ATD0CTL3 = 0x42;
    ATD0CTL4 = 0x21;
     PORTA_BIT1 = 0x01;
  }


  void AD1_Config()
  {
    ATD0CTL2 = 0xc2;
    ATD0CTL3 = 0x42;
    ATD0CTL4 = 0x21;
     PORTA_BIT2 = 0x01;
  }



#pragma push
#pragma CODE_SEG __NEAR_SEG NON_BANKED

__interrupt void _AD0Conversion(void){

extern int one;
extern int two;     
extern int three;
extern int four;
extern int five;
extern int six;
extern int seven;
extern int eight;


one =ATD0DR0;          
two = ATD0DR1;  
three = ATD0DR2;  
four = ATD0DR3;  
five = ATD0DR4;                      
six = ATD0DR5;
seven = ATD0DR6;  
eight = ATD0DR7;
  PORTA_BIT3 = 0x01;

}

#pragma pop

#pragma push
#pragma CODE_SEG __NEAR_SEG NON_BANKED

__interrupt void _AD1Conversion(void){

extern int one1;
extern int two1;     
extern int three1;
extern int four1;
extern int five1;
extern int six1;
extern int seven1;
extern int eight1;


one1 =ATD1DR0;          
two1 = ATD1DR1;  
three1 = ATD1DR2;  
four1 = ATD1DR3;  
five1 = ATD1DR4;                      
six1 = ATD1DR5;
seven1 = ATD1DR6;  
eight1 = ATD1DR7;
  PORTA_BIT4 = 0x01;

}

#pragma pop




void main(void) {
DDRA = 0xFF;
PORTA_BIT0 = 0x01;

AD0_Config();
AD1_Config();


EnableInterrupts;

  for(;;) {} /* wait forever */
  /* please make sure that you never leave this function */
}





//extern void near _Startup(void);       /* Startup routine */                               


#pragma push
#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
__interrupt void _AD0Conversion(void);
__interrupt void _AD1Conversion(void);
__interrupt void UnimplementedISR(void)
{
   /* Unimplemented ISRs trap.*/
}
#pragma pop

typedef void (*near tIsrFunc)(void);
const tIsrFunc _vect[] @0xFF80 = {     /* Interrupt table */
        UnimplementedISR,                 /* vector 0x40 */
        UnimplementedISR,                 /* vector 0x3F */
        UnimplementedISR,                 /* vector 0x3E */
        UnimplementedISR,                 /* vector  0x3D */
        UnimplementedISR,                 /* vector 0x3C */
        UnimplementedISR,                 /* vector 0x3B */
        UnimplementedISR,                 /* vector 0x3A */
        UnimplementedISR,                 /* vector 0x39 */
        UnimplementedISR,                 /* vector 0x38 */
        UnimplementedISR,                 /* vector 0x37 */
        UnimplementedISR,                 /* vector 0x36 (PWM Emergency Shutdown) */
        UnimplementedISR,                 /* vector 0x35 (Port P Interrupt) */
        UnimplementedISR,                 /* vector 0x34 (CAN4 Transmit) */
        UnimplementedISR,                 /* vector 0x33 (CAN4 Receive)  */
        UnimplementedISR,                 /* vector 0x32 (CAN4 Errors)   */
        UnimplementedISR,                 /* vector 0x31 (CAN4 Wake-Up)  */
        UnimplementedISR,                 /* vector 0x30 (Reserved) */
        UnimplementedISR,                 /* vector 0x2F (BF General)         */
        UnimplementedISR,                 /* vector 0x2E (BF Synchronization) */
        UnimplementedISR,                 /* vector 0x2D (BF Receive)         */
        UnimplementedISR,                 /* vector 0x2C (BF Receive FIFO Not Empty) */
        UnimplementedISR,                 /* vector 0x2B (CAN1 Transmit) */
        UnimplementedISR,                 /* vector 0x2A (CAN1 Receive)  */
        UnimplementedISR,                 /* vector 0x29 (CAN1 Errors)   */
        UnimplementedISR,                 /* vector 0x28 (CAN1 Wake-Up)  */
        UnimplementedISR,                 /* vector 0x27 (CAN0 Transmit) */
        UnimplementedISR,                 /* vector 0x26 (CAN0 Receive)  */
        UnimplementedISR,                 /* vector 0x25 (CAN0 Errors)   */
        UnimplementedISR,                 /* vector 0x24 (CAN0 Wake-Up)  */
        UnimplementedISR,                 /* vector 0x23 (FLASH) */
        UnimplementedISR,                 /* vector 0x22 (EEPROM) */
        UnimplementedISR,                 /* vector 0x21 (Reserved) */
        UnimplementedISR,                 /* vector 0x20 (SPI1) */
        UnimplementedISR,                 /* vector 0x1F (IIC Bus) */
        UnimplementedISR,                 /* vector 0x1D (BDLC) */
        UnimplementedISR,                 /* vector 0x1C (CRG PLL Lock) */
        UnimplementedISR,                 /* vector 0x1B (Pulse Accumulator B Overflow) */
        UnimplementedISR,                 /* vector 0x1A (Modulus Down Counter Underflow) */
        UnimplementedISR,                 /* vector 0x19 (PORT H) */
        UnimplementedISR,                 /* vector 0x18 (PORT J) */
        _AD1Conversion,        /* vector 0x17 (ATD1) */
        _AD0Conversion,        /* vector 0x16 (ATD0) */
        UnimplementedISR,                 /* vector 0x15 (SCI1) */
        UnimplementedISR,                 /* vector 0x14 (SCI0) */
        UnimplementedISR,                 /* vector 0x13 (SPI0) */
        UnimplementedISR,                 /* vector 0x12 (Pulse Accumulator Input Edge)  */
        UnimplementedISR,                 /* vector 0x11 (Pulse Accumulator A Overflow)  */
        UnimplementedISR,                 /* vector 0x10 (TOF, timer overflow interrupt) */
        UnimplementedISR,                 /* vector 0x0F (C7I, timer interrupt channel 7)  */
        UnimplementedISR,                 /* vector 0x0E (C6I, timer interrupt channel 6)  */
        UnimplementedISR,                 /* vector 0x0D (C5I, timer interrupt channel 5)  */
        UnimplementedISR,                 /* vector 0x0C (C4I, timer interrupt channel 4)  */
        UnimplementedISR,                 /* vector 0x0B (C3I, timer interrupt channel 3)  */
        UnimplementedISR,                 /* vector 0x0A (C2I, timer interrupt channel 2)  */
        UnimplementedISR,                 /* vector 0x09 (C1I, timer interrupt channel 1)  */
        UnimplementedISR,                 /* vector 0x08 (C0I, timer interrupt channel 0)  */
        UnimplementedISR,                 /* vector 0x07 (RTIE - Real-Time Interrupt) */
        UnimplementedISR,                 /* vector 0x06 (IRQ)  */
        UnimplementedISR,                 /* vector 0x05 (XIRQ - External Interrupt) */
        UnimplementedISR,                 /* vector 0x04 (SWI - Software Interrupt)  */
        UnimplementedISR,                 /* vector 0x03 (Unimplemented Opcode Trap) */
        UnimplementedISR,                 /* vector 0x02 (COP Watchdog Reset)        */
        UnimplementedISR,                 /* vector 0x01 (Clock Monitor Reset)       */
        //_Startup                          /* vector 0x00 (Power-On/Staru-Up RESET)   */
   };



  

Have any ideas? I am quite certain that the interrupts are not executing because I have set LEDs to illuminate within the A to D ISRs. These LEDs are never illuminated during debugging nor do any of my A to D variable show any value other than 0. When I configure the A to D registers to be non interrupt based I have no issues.Any thoughts as to why my interrupts are not working? Are these type of interrupts supported in Serial Monitor? Any help or hints would be great. I have been fighting this for the last few days.

 

Thanks,

Pete

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