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HCS08SG16/32 internal clock setting / divider problem

Question asked by Thomas Haertling on Oct 27, 2009
Latest reply on Oct 29, 2009 by Thomas Haertling


I am new to this forum and have a question to the internal clock and I hope, someone can help me.


First, my environment:

Codewarrior 6.2.2

Demoboard DEMO9S08SH32/SG32


What I want:

I want a CPU - clock of 4 MHz


What I did:

setting ICSC1 to 0x06

(clock source = FLL, Reference divider = 000, Internal reference select = 1, internal refence clock enable = 1, internal reference Stop Enable = 0)


setting ICSC2 to 0xC0

(Bus frequency divider = 11 -> divide by 8)


my calculation for this setting:

the FLL multiplies the 31.25 kHz by 1024, so I get a internal fequency of 32 MHz, then divide by 8 -> so I have 4 MHz.

(according to the datasheet in the system clock distribution diagram the cpu is connected to ICSOUT and not to BUSCLK)


I checked the cpu frequency in the following way:


I toggle a port:


    asm BSET 5, 0x02
    asm BCLR 5, 0x02
    asm BSET 5, 0x02
    asm BCLR 5, 0x02
    asm BSET 5, 0x02
    asm BCLR 5, 0x02


And then I measure the time between 2 rising edges. The BSET and BCLR instruction takes 5 cycles each.  I measured a time of 5 us (for the 10 cycles between 2 rising edges). So I have a cpu clock of 2 MHz (0,5 us Periode).


Does anybody know, where the additional divide by 2 comes from? I assumed a clock of 4 MHz.


have a nice evening,










// select internal reference
// activate ICSIRCLK (internal reference Clock enable)
  ICSC1 = 0x06;

// Bus frequency divider = 1

  ICSC2 = 0xC0;




I tried to check the cpu clock.

I use the internal reference and the FLL, so I ge