I'm currently working on some code to interface a GPIO extender with a 5484 custom board running a Linux provided by Freescale (LTIB). I'm using spidev driver but got some issues to make it work properly. Indeed when I'm sending N bytes to the SPI and monirtoring the signals on an oscilloscope I can see the following :
- The N-1 first bytes are sent one after the other with CS asserted. SPI clock is ticking
- CS gets deasserted during a few µs. No clock
- The last byte is then sent with CS asserted and SPI clock ticking
This is quite a problem for me as the GPIO chip interprets the CS deassertion as the end of the current message so that the chip sees one N-1 bytes long message and a second one of one byte.
Running the example provided by LTIB (SDI and SDO tied together to write and read back the message) with spi_test, I can see the same behaviour.
In my code, I'm initializing a spi_ioc_transfer with the cs_change = 0 so that the deassertion of CS should not happen.
Does anyone know where this behaviour comes from and how to avoid CS from being deselected in the middle of a message ?
Thank you a lot !