Instruction cache activation with DRAM for MCF54455

Discussion created by mehrdad on Oct 16, 2009
Latest reply on Dec 23, 2010 by McuG



I have a custom board which is similar to Freescale evaluation board for MCF54455. If I don't activate instruction cache on DRAM, everything running. However when I activate the instruction cache the code stops when start running from DRAM.


I used BDM to investigate. If the instruction is more than 32 bit, then the next data for instruction comes from different address and not the next 32 bits. Of course when instruction cache is not active everything is fine. I even removed DRAM address from ACR registers but still happening. By just activating cache this will happen.


Any help will be appreciated.