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MC9S08JM60 - internal workings of the automated FLASH page erase mechanism

Question asked by Ronald Steger on Aug 28, 2009
Latest reply on Aug 29, 2009 by kef



I'm currently working on driver for EEPROM emulation using the flash array in a MC9S08JM60 chip. The data is critical in our application, and must be correctly recoverable given that we may have a power loss at any time. So we work with multiple flash pages used in a circular manner, and use a make-before-break algorithm. We activate the LVD reset, to avoid brown out problems.


My questions:


1. The datasheet talks about flash access errors and flash operation aborts when entering stop mode during execution of a flash command. What happens with the internal flash state machine when the MCU is reset, for example, by the LVD system? Is the operation aborted, as one would assume?


2. Does the internal flash state machine erase data within a page in a particular order? Are flash pages erased one byte at a time starting at the lowest address? Or one 64-byte row at a time? Or is erase voltage applied to the whole 512-byte page at once?


Once the erase mechanism is understood, we can know what to expect if we suffer a power loss while a page is being erased. We can know what part of the data is gone first. This is important for the correct placing of metadata within a page, as well as for the correct interpretation of the results of a partial page erase aborted by a power failure.


I've gone over the datasheet and the reference manual but was unable to find this information. I probably need information from a Freescale product engineer.


Thanks in advance,