Sevak Kumbhare

PLL issue in MC68HC980

Discussion created by Sevak Kumbhare on Aug 13, 2009
Latest reply on Aug 13, 2009 by Sevak Kumbhare


      I am facing a problem with PLL. In Normal operation after stabilising crystal clock i am switching to VCO clock as a base clock. After this, I hope that LOCK bit should not toggle as crystal frequency is stabilised. But in practical scenario i am observing that this LOCK bit is toggling.


Can anyone please tell me why this is happening? Will VCO frequency move out of specified range in normal operation?