I have read most of the SPI discussions, but it seems the ony functional use of the SPTEF bit is for double buffered transmit operation. I know the SPTEF must be read while high before writing to the SPID to start a transfer and the SPRF being the transfer complete flag. For an interrupt driven SPI application, what function does the SPTEF bit serve besides double buffered use? It seems the SPI receive full interrupts need only to be enabled (assuming mode fault is not used). I will post up my code shortly which will explain this.
Second question. Does the SPTEF bit actually become low when the SPI transmit buffer is full?
Lets there are back to back SPI transfers. For the idle SPI, the SPTEF bit will set within 2 bus cycles. The second SPID write should clear the SPTEF bit since the SPI shift register contains the first byte.