A couple of questions:
Is 115200bps baurate is supported for MC9S12E64? I'm using a 29.4912mhz crystal freq. the calculated divisor is 8. No PLL.
What's the minimum baudrate divisor for SCI?
The Reference Manual says:
"The value from 0 to 8191 written to the SBR12–SBR0 bits determines the module clockdivisor.
SCI baud rate = SCI module clock / (16 * SCIBR[12:0]) "
.. which seems to say that 115.2kBd is achievable. And, in the case of a 29.412MHz clock,
the baud-rate error is 0%:
115,200 = (29.4912e6/2) /(16 * D) ===> D= 8.000
For a 25MHz clock, the nearest baud-rate to 115.2k is
(25e6/2 )/(16*7) = 111.6kBd... which is slow by about 3%, but works flawlessly
(for desktop debug distances, anyway) on my ne64 boards
Thank you Wade. So the answer is yes. I was asking this because some microcontrollers limit they baudrate by 0.x rate of the frequency bus, and I didn't find any other restriction on the Manual.
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