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MCC syncronization pattern, MPC8560

Question asked by Gleb Krylov on Aug 6, 2009
Hello all!

Did anyone set receive syncronization in MCC by pattern?
(p. 33-15, MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual, Rev. 1)

chamr = 0x7200, Transparent, Enabled pooling, SYNC=b10 (Receive - 8-bit, Transmit - none).
zdstate = 0x00000000, because RCVSYNC = 0bxxxx_xxxx_xxxx_xxx1, Regular order.
RCVSYNC = 0x9b - syncronization pattern.
This results to no interrupt generation, I don't know why at the moment.

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