System Clock Calculation Confusion

[GaryOlmstead]

Hi --

I have a MCF52259 that will have Ethernet, USB, and RS-485 ports.  I would like to use a single clock source for all three.  USB requires 48 MHz exactly, Ethernet seems to be happy with anything over 50 MHz, RS-485 should be 57600, although adjacent rates will do if necessary.  So, I need to balance MFD, RFD, and CCHR.

My problem is that I can't find values for MFD, RFD and CCHR that yield a value between 50 and 80 MHz, and will also yield an integer remainder after being divided by 32 for the baud rate generator.  I have two questions for you.

One, what is the purpose of Table 7-6 on page 136 of the Reference Manual?  It shows the ratios for every value of MFD divided by every value of RFD, but that ratio isn't used in the calculation of Fsys, or anyplace else I can find.  Is the table a red herring, or is the formula for Fsys wrong?

Two, the Fsys calculation appear to generate very few useful values.  In particular, Fsys for RFD = 4 to 7 is anywhere from zero to a few kiloHertz.  Fsys for RFD of 0 or 1 quickly runs over 80 MHz.  Is this correct, or is the formula for Fsys wrong, or did I mess up the calculation?  I put it in a spreadsheet, but I have no idea how to post it here.

Thanks

Gary Olmstead

[eGuy]

Gary,

I didn't see problems in Table 7-6.

Using 48Mhz external oscillator, for example, if you want to get PLLed 56Mhz fsys, you can do this:

1) set CCHR = 5, this gives you fref = 48/(1+5) = 8Mhz ( see 7.7.1.5).  fref is PLL reference clock.

2) set RFD =000 (PLL divisor is 1), MFD=010(PLL multiplication factor=8), 

      fsys = fref x 2(MFD+2)/pow(2,RFD) = 8 x2(2+2)/pow(2,0)=8x2x4/1=8x8=64Mhz.

     ( from Table7-6 you can easily get multiplier 8 )

For your reference:

In 52259EVB board, MQX OS set system clock to 80MHz. the code snippet is below ( ...\bsp\m52259evb\bsp_init.c) 

    /*

     ** Divide 48Mhz reference crystal by 6 and multiply by 10 to achieve a
    ** system clock of 80 Mhz.
    */
   
    reg_ptr->CLK.OCLR  = 0xf0;
    reg_ptr->CLK.CCHR  = 5;
    reg_ptr->CLK.SYNCR = 0 |
        MCF5225_CLOCK_SYNCR_RFD(0) |
        MCF5225_CLOCK_SYNCR_MFD(3) |
        MCF5225_CLOCK_SYNCR_PLLMODE|
        MCF5225_CLOCK_SYNCR_PLLEN;

Message Edited by eGuy on 2009-07-23 04:18 PM

[GaryOlmstead]

Hi --

Well, without reproducing my whole spread sheet here, let me summarize it.  For a 48 MHz crystal, and CCHR = 5, of the 64 possible values for Fsys, only five are between 50 and 80 MHz.  Not counting duplicated entries, there are only three different values between 50 and 80 MHz.  Other values for CCHR give similar results, as does lower crystal frequencies.

Even if you give up Ethernet's greater than 50 MHz requirement, about half the answers are for Fsys less than 1 MHz, and about a quarter are for Fsys less than one Hertz.  Not very useful.

I guess I was surprised by this because Motorola/Freescale parts in the past have scalar values that give results that are at least mostly within range.  But these just seem to be numbers drawn out of a hat.  They generate Fsys values that aren't even remotely plausible.

[GaryOlmstead]

Some more playing with the numbers gives me a useful answer.  Setting CCHR to 6, MFD to 6, and RFD to 2 gives Fsys = 72 MHz, and a baud divisor of 39.06.  Using 39, the baud rate error is 0.16% which is fine.  But that doesn't explain why there are so few usable values.