hc08 monitor mode question

[voltaic]

According to the HC08QY series datasheets, they have an internal charge pump to program the flash memory.  Also, according to the datasheet an external high voltage is absolutely required on one of the pins in order to get it into normal monitor mode.

why would the externally applied high voltage need to be present if it has an internal charge pump to generate the same high voltage?  this does not make sense to me.  why not just generate the voltage for programming in monitor mode internally, and save me the trouble of doing it?

thanks!

-Sam

[OmarAI]

Dear Voltaic,

                 I don't really know why the mcu needs an external high-voltage entry in the IRQ pin, but according to the HC08QY datasheet, the internal charge pump works when the flash memory needs to be programmed or erased, so it seems to me that this voltage it's not always "present" inside the mcu (goes on and off according to what is doing). Take a look at this paragraph I've copied from the datasheet:

"  Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR).
   The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM
operations.  " 

            May be it is related to that same protection system the flash memory has. Besides, the high voltage needs to be on all the time when in monitor mode and if you need to program or erase the flash memory (turn on and off those 9.1V) you would have to exit monitor mode at some point (as IRQ will loose its high voltage entry) of the programming and debugging procedure, what, as far as I know is not possible. 

            I personally think that if Freescale's designers thought that the high voltage entry needs to be external despite the internal charge pump they must have had a good reason (or at least I hope so!), so we should think that they've used the most suitable designing technique focused on performance and reliability.

Regards, Omar.

Message Edited by OmarAI on 2009-06-24 02:50 AM

[bigmac · Accepted solution]

Hello Sam,

For HC908 devices, and following a POR, if the device has not been previously programmed, i.e. the reset vector at address 0xFFFE is unprogrammed, monitor mode will be entered without the need for high voltage on the IRQ pin.

However, if the device has previously been programmed, there needs to be a way of communicating to the device that the normal reset procedure should not be followed, and that monitor mode should be entered. This includes the application of a high voltage to the IRQ pin, a condition that should never be present during normal operation.  It also requires that some other pins should be at specific states - I do not know the reason for this additional requirement.

For the QT/QY devices (and many other small devices with limited RAM size), additional monitor ROM exists, and routines within this ROM are used for flash erase and programming operations.  It is these routines that control the HVEN bit (and the charge pump), along with other critical timing requirements.

Of course, this explanation applies only for the older HC908 family, and is not applicable to the more recent HCS08 family.

Regards,

Mac

[voltaic]

Thank you for your replies everyone!

-Sam

[celsoken]

Dear Voltaic,

I think I should leave this answer for a freescaler, but as far as I remember the Qy samples the high voltage at power on reset in order to activate MON mode,  charge-pumps take some time to engage... I remember the old 05s that had this characteristic.

Personally, I would not like to have charge pumps running when my normal software is running, seems to raise possibility of (unwanted) flash operations, creating a catastrophic failure mode.

Cheers,

Celso