I designed this into a new product or ours.
I notice that the chip frequently results in an I2C bus stuck event that needs recovery.
This occurs when writing the control register for a MUX selection, followed immediately bu a read to confirm the correct selection.
The bus will sometimes become stuck in that SDA remains low forever or until bus recovery procedure.
The bus become stuck at around bit 8 or Ack of read data address. See attached wave capture.
This happens at a frequency of around 1 in 1000 or in my case about every 3 minutes.
Bus operation is 100kHz.
What can cause this problem?
The bus signals are clear and beautiful. Is there a minimum time specification between a write followed by read ?
I cannot see it in the datasheet.