I am trying to test error handling for DCache ECC errors in bare-metal (running at EL3) on a LS1043ARDB.
If I set CPUACTLR_EL1.L1DEIEN (bit) and then write a cacheable location, nothing seems to happen.
The CPUMESSR doesn't change, nor is there an abort, etc.
I have also tried L2 (L2ACTLR) and caused an eviction from L1.
I can see the data is in the cache by reading the cache RAM.
I feel like I am missing some other enable somewhere?