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How to enable error injection on LS1043A DCache

Question asked by Alan Ross on Jul 29, 2020
Latest reply on Aug 2, 2020 by ufedor

I am trying to test error handling for DCache ECC errors in bare-metal (running at EL3) on a LS1043ARDB.

If I set CPUACTLR_EL1.L1DEIEN (bit[6]) and then write a cacheable location, nothing seems to happen.

The CPUMESSR doesn't change, nor is there an abort, etc.

I have also tried L2 (L2ACTLR[29]) and caused an eviction from L1.

I can see the data is in the cache by reading the cache RAM.

I feel like I am missing some other enable somewhere?

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