Illegal Memory Access and Illegal instruction handling

[pratibhasurabhi]

Hi All,

I am using S12 ZVML microcontroller.

I wanted to know whether there is any specific handling for illegal memory access and illegal instruction execution.

I checked the memory mapping control Module [MMC] in the RM. From it, I understand Machine exception is issued for an illegal access. The cause can be verified by looking at the Error code register [MMCEC]. And further safe handling once exception is issued can be to forcibly perform WDT reset.

Can anyone please guide me about behaviour and handling when illegal instruction is executed.

Thank you.

[RadekS]

Hello Pratibha,

More details regarding Machine exception may be found in S12ZCPU reference manual:

https://www.nxp.com/webapp/Download?colCode=S12ZCPURM

Please be aware, that the machine exception recovery process is fully user-dependent.

The difference between standard interrupt and machine exception:

• The Machine Exception is non-maskable.
• A Machine Exception is considered a severe system error, so nothing (like CPU registers and return address) is written on the stack.
• The MMC module saves only information about the S12Z CPU state which otherwise would be lost due to exception processing (e.g. the Program Counter register and X-, I- and U-bits from the Condition Code Register).

Since there isn’t a return address on the stack, the standard RTI instruction cannot be used for the end of the machine exception routine. You may end the machine exception routine either by any MCU reset or by a jump to any known address in the code.

For the second case, be aware that both the X- and I-bits are set and the U-bit is cleared during entering of machine exception. By some known address I mean for example Startup() address, some machine exception recovery function address (which manage maintenance like motor stop, wait for store EEPROM data, notification to the upper system,…) or the address calculated from PC value stored in MMC registers. The last option (the address calculated from PC value stored in MMC registers) is possible, but I cannot recommend it for any use except testing.

You may look at my example codes focused on ECC as the machine exception source:

https://community.nxp.com/docs/DOC-334381

https://community.nxp.com/docs/DOC-334327

https://community.nxp.com/docs/DOC-344440

https://community.nxp.com/docs/DOC-334328

https://community.nxp.com/docs/DOC-333148

I hope it helps you.

Best regards

Radek

[pratibhasurabhi]

Hi RadekS‌

Thank you.

So does it mean even illegal instruction execution will lead to issuance of machine exception?

[RadekS]

Hello Pratibha,

sorry for my misleading answer, I didn't read your question enough carefully.

You are right, the illegal access causes Machine Exception.

While the illegal instruction causes either SPARE or TRAP interrupt.  

In these cases, standard CPU content (registers and return address) is stored on the stack. That allows founding illegal instruction (called unimplemented opcode) and their address (located at the two bytes before the return address).

Two interrupts are implemented to distinguish between page 1 and page 2 of the instruction set.

Similar to machine exception, the content of the interrupt routine is user-dependent. The option may be for example the full stop of operation, switch to a safe state, just notification to the upper system, or simply continue in operation (RTI works in this case)...

Both SPARE and TRAP interrupts also allows change the user state to the supervisor state. So, if you use user state in your application, the supervisor state in interrupt will allow you the operations with CCR register.

I hope it helps you.

Best regards

Radek

[pratibhasurabhi]

Hello RadekS‌

Thank you for your reply.

I understood the behaviour when illegal instruction is executed - SPARE or TRAP interrupt.

Can you please suggest testing method to invoke either SPARE or the TRAP interrupt through illegal instruction execution

Thank you

[RadekS]

Hello Pratibha,

Sorry for my late response.

Please look at table Table A-2. Opcode Map in S12ZCPU RM.

The SPARE interrupt will be caused by instruction 0xEF.

The TRAP interrupt will be caused for example by instruction 0x1B FF.

In general, you may create array in RAM, jump to it and execute your code, and finally return back to your code.

Unfortunately, I didn’t test it (I don’t have any S12Z board here), but you you may try something like this:

//variable declaration

volatile usingned char my_code_SPARE[2]={0xEF, 0x05}  //0xEF is unimplemented opcode from page 1, 0x05 is opcode for RTS
volatile usingned char my_code_TRAP[3]={0x1B, 0xFF, 0x05} //0x1B FF is unimplemented opcode from page 2, 0x05 is opcode for RTS‍‍

//in main()

asm JSR my_code_SPARE;
asm JSR my_code_TRAP;‍‍

Note: Please ensure in map file that above mentioned variables were not optimized out by linker as unused (linker typically ignore your variable use in assembler code). If yes, please enter variable names into ENTRIES senction in your prm linker file. With that, the variables will stay in memory without optimization. 

I hope it helps you.

Best regards

Radek

[pratibhasurabhi]

Hello RadekS‌

Thank you for the reply.

I want to test the illegal access fault by generating illegal access.

Can you please suggest testing method to invoke machine exception through illegal access.

Thank you.

[RadekS]

Hi Pratibha,

Please look at Table 3-9. Illegal memory accesses in S12ZVM RM.

The table show list of memory accesses with the classification of illegal type.

For example:

• execution from register space (e.g. jump to address 0x000000)
• any access to Unmaped space (e.g. read/write/jump to address 0x200000) 
• ...

I hope it helps you.

Best regards

Radek

[pratibhasurabhi]

Hi Radek,

Thank you for the reply.

I want to test the illegal access fault by generating illegal access.

Can you please suggest testing method to invoke machine exception through illegal access.

Thank you.