I'm developing a board with LS1046A. I would like to use LS1046A DDR controller using x72 data bus: x64-bit data and x8-bit ECC. As a guide, I've seen the scheme of DDR4 in FRWYLS1046A-PA, so 4 DDR4 devices are used for data and one DDR4 device is used for ECC.
In our case, we are considering the use of DDR4 MT40A256M16LY-062 IT from Micron.
Regarding the design of FRWYLS1046A-PA and the use of MT40A256M16LY-062, I have certain doubts after reading AN5097 application note:
1) Item no. 8 and 9: in the VTT island it is recommended the use of one low ESL capacitor for each group of four termination resistors, at least one 4.7uF cap and a bulk capacitor (47 - 220 uF) at each end of the VTT island.
However, in FRWYLS1046A-PA I only see two capacitors of 10 uF connected to DDR_VTT (VTT Power supply). Additionally, there is a capacitor network used to decouple DDR_VTT( VTT Power supply) from GVDD (LS1046A DDR controller and DDR4 VDD power supplies). (Figure below)
So, which is the best way for decoupling the VTT island? Only acccording to AN5097 recommendations or including both methods?
Is it necessary to decouple DDR_VTT from GVDD? I don't find anything about this in NXP or Micron datasheets.
2) Item no. 60: it is stated to pull-up the eight unused DQ pins when 16-bit DRAM is used for ECC. On the other hand, TN4041 application note from Micron recommends to leave those pins unconnected. This last case is implemented in FRWYLS1046A-PA. Are both type of connections valid? Which is the best solution?
Thank you in advance for your help.