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RT1020/RT1050 ref manual issue?: BT_MPU_DISABLE and L1 I-Cache DISABLE fuses.

Question asked by rshipman on Jul 11, 2020
Latest reply on Jul 12, 2020 by fangfang



In the manual:

i.MX RT1020 Processor Reference Manual, Rev. 1, 12/2018

Table 21-9. Fusemap Descriptions

Page 1116


The table specifies:



0x470[2] L1 I-Cache DISABLE


However in the tables:

Table 21-2. FlexSPI (Serial NOR) boot fusemap, page 1098

Table 21-3. SD boot fusemap, page 1100

Table 21-4. MMC/eMMC boot fusemap, page 1102

Table 21-5. SEMC (NAND) boot fusemap, page 1103

Table 21-6. SEMC (NOR) boot fusemap, page 1105

Table 21-7. FlexSPI1 (Serial NAND) boot fusemap, page 1106


The tables show:


0x470[1] L1 D-Cache DISABLE

0x470[2] L1 I-Cache DISABLE


So what does 0x470[1] actually do?


The same issue exists in the RT1050 Reference Manual as well, so if this is a mistake, it might be worth checking the RMs of all similar devices:

i.MX RT1050 Processor Reference Manual, Rev. 3, 8/2019


Kind regards,