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T1042D4RDB SerDes Memory Mapping

Question asked by on Jul 12, 2020
Latest reply on Jul 13, 2020 by



I'm working with u-boot on T1042D4RDB, and have some question about SerDes memory mapping.


  1. Is there a maximum physical memory region which is allocated by CPU for SerDes ? If so, is there any documentation about CPU physical memory mapping limits?
  2. If SerDes has a maximum physical memory region, can i set custom size TLBs and LAWs inside this memory region? For example, according to 0x06 SerDes configuration, SerDes has 4 PCIe buses. Can these buses have custom-size memory regions? Is there any constraint about minimum size or maximum size for each bus?
  3. Does maximum SerDes memory region depend on CPU or board? I mean, is it configurable size from board to board?


Thanks in advanced.