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The power domains with MIPI in IMX7S: 1V rail and decoupling caps

Question asked by Andy Hall on Jul 8, 2020
Latest reply on Jul 15, 2020 by Andy Hall

We are using the IMX7Solo in a display project.


We use the MIPI interface to talk from the Solo to our display driver bridge chip. When the processor is powering up, all goes well until the LDO_1P0D is powered up. Then the processor hangs.


Stepping through the assembly code, it gets no further than enabling this regulator.


Enabling the current limit feature of the internal regulator, the processor can get past this stage. Enabling the brown out detect, shows that there is a brown out. However this internal power rail is only connected externally to the advised capacitors (as per the datasheet) and the two VDD_MIPI_1P0 pins, nothing else.


We have also found that if power up the 1V0 (with current limiting) then the internally switched 1V8 sometime later, the processor hangs again. So even with the current limiting on there, enabling the 1V8 rail after the 1V rail causes an issue with the supplies.


We are currently working in the belief that there is an issue where the inrush current on the 1V rail causes the power rail to drop significantly.


What can we do to limit the current draw on the 1V rail when we have no control over what it's connected to (other than the advised decoupling capacitors)?


We cannot see any advice on how the IMX7Solo decoupling requirements differ to the IMX7Dual, despite the fact that the Solo does not have the PCIe module, which (in the Dual) uses the 1V0 rail as well. This processor has no efuses blown, currently booting from the SD card.