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imx7d using dma to transfer eim data

Question asked by 其东 刘 on Jul 8, 2020
Latest reply on Jul 8, 2020 by igorpadykov

Hello everyone
my development board is IMX7DSABRE. Linux kernel version is 4.9.88.
When I use dma to transmit EIM data to FPGA on imx7d, when I write data to EIM bus, some problems occur. My EIM bus data width is configured to 16bit, I write 16 bytes of data to the bus each time:
0x1234 0x1235 0x12346 0x1237 0x1238 0x1239 0x123a 0x123b
My FPGA can receive these 16 bytes of data, but it also receives an additional 16 bytes of 0 data. The 0 data was received because the EIM bus generated 8 more write signals.
Normally, according to the configuration of my data line width, when 16 bytes occur, only 8 write signals need to be generated, but actually 16 write signals are generated. The waveform diagram is as follows:


My dma code configuration is as follows:
dma_m2m_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
dma_m2m_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
dma_m2m_config.src_maxburst = EIM_WRITE_SIZE/2;
dma_m2m_config.dst_maxburst = EIM_WRITE_SIZE/2;
dmaengine_slave_config(dma_m2m_chan, &dma_m2m_config);
dma_m2m_desc = dma_m2m_chan->device->device_prep_dma_memcpy(dma_m2m_chan, dma_dst, dma_src, length, DMA_MEM_TO_MEM);

 

I want to know why there are 16 write signals?

At the same time I tried to configure different values for dst_addr_width and src_addr_width, but no matter how I configure it, there will always be redundant write signals. How should I solve this problem?

 

At the same time I tried dst_addr_width and src_addr_width to configure different values, such as:
dma_m2m_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
dma_m2m_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;


dma_m2m_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
dma_m2m_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;


dma_m2m_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
dma_m2m_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;


dma_m2m_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
dma_m2m_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;


dma_m2m_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
dma_m2m_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;


dma_m2m_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_m2m_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;


dma_m2m_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_m2m_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
But no matter how I configure it, there will always be redundant write signals. How should I solve this problem?

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