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Voltage drop every adc trigger

Question asked by Francis Yeung on Jul 7, 2020
Latest reply on Jul 22, 2020 by Francis Yeung

Currently I am using LPC5528, I have to do 1M sample/s ADC sampling continuously, keep streaming out the value.

 

I attach 96M HF clock to adc with divider = 4, STS = 3, 16bit resolution.

loop cnt = 15, it will do 16 times sampling/conversion for each trigger, and write to FIFO0 and FIFO1 alternately

 

My implementation is, 

  1. Init, sw trigger adc to write to FIFO0
  2. FIFO0 full -> adc isr
  3. in adc isr, sw trigger adc to write to FIFO1 and trigger DMA to copy from FIFO0 to memory
  4. FIFO1 full -> adc isr
  5. in adc isr, sw trigger adc to write to FIFO0 and trigger DMA to copy from FIFO1 to memory
  6. FIFO0 full -> adc isr
  7. repeat 3 - 6

 

there is a delay between each trigger, around 1us. 

i.e. if i feed a sine wave to the adc pin, the line is not smooth at every 16 sample. 

Please see Figure 1

 

More importantly, there is a voltage drop when the adc start, we can always see a smaller value in FIF0 1st entry. 

I know the ENOB of LPC5528 16bit resolution is 12bit. But the drop is out of this range. And it happens every 16 values, so it must be related to the MCU, not a random noise.

Please see Figure 2

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