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PMIC_ON_REQ behavior during CPU POR

Question asked by Harsh Mistry on Jul 7, 2020
Latest reply on Jul 17, 2020 by igorpadykov



We are designing a custom board using i.MX 8 DualXPlus CPU based on the  i.MX 8QXP MEK board.

In order to simplify the Reset Scheme, we are doing the following changes:

1.  The SCU_WDOG_OUT and PMIC_WDOG_IN is bypassed (connected directly).

2.  PMIC_POR_B_1V8 is logically ANDed with the supervisory circuit as shown in the attached image:



We have two questions:

1. In the event of pressing the manual reset button SW1, it will drive MANUAL_RESET to 0V eventually driving POR_B_1V8 to 0V so that the processor resets. During this, does the PMIC also perform a reset operation ( complete power cycle of all regulators)?


2. What will be the behaviour of PMIC_ON_REQ signal from the processor in the above event?