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i.MX 8M Quad synchronous EA on GPC access from EL0

Question asked by stefankalkowski on Jul 7, 2020
Latest reply on Jul 27, 2020 by Luis Perez

Hi all,

 

I currently implement an i.MX 8M platform driver for the component-based Genode OS framework. It is a microkernel architecture, and drivers are simple applications executed in EL0. I could sucessfully use the driver already to configure, e.g., the Clock Control Module (CCM). However, when I access certain registers of the General Power Controller (GPC) I receive an synchronous external data-abort. I can successfully access the general configuration registers of the same GPC MMIO region (everything in between 0x303a0000-0x303a0250), but if I read/write the Power Gating Controller (PGC) registers of any power domain (>= 0x303a0800), I encounter a synchronous EA.

The curious thing about it is whenever I do the same accesses in EL1 in the kernel, I can successfully power up/down the corresponding domains without failure. Therefore, I was suspecting some of the security modules in the SoC, like AIPSTZ1-4, or the Central Security Unit (CSU) to prohibit the EL0 access. However, they are configured by the ARM Trusted Firmware (ATF) to allow any access, also normal-world, unprivileged one. I can read those CSU and AIPSTZ registers, and see they are locked but allow any access.

Of course, I can build a work-around to either do the GPC access, or call the ATF within the kernel. However, it somehow hits the otherwise pure design.

But foremost, I would like to understand which mechanism in the SoC returns the bus-error in my use-case?

 

Any clarification is highly appreciated. Thank you in advance.

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