I am working on imx6Q pcb board and I would like to use 4 DDR3 chips in fly-by topology.
In the 3.7§ DDR power recommendations of the Hardware Development Guide, NXP tells about DDR_VTT. I read articles and documentations which specify to use SW4 VTT mode.
I want to use the PMIC0100 chip in default mode.
1_ Does the VTT island can be provided by the VREFDDR pin (pmic)?
Also the number of decoupling capacitor is not clear.
2_ How many decoupling capacitors need to be placed on VTT island?
I saw Open Source project with decoupling capacitor between VTT and GND and between VTT and DDR_1.5V
3_ Did the last decoupling capacitor between VTT and DDR_1.5V is required ?
Hope someone could help me.