I'm trying to enable the Watchdog timer on the SCU of a custom iMX8QM design.
The iMX8QM Reference Manual (rev F) states that:
13.9.3 Application Information
The watchdog is enabled by default after reset. [...]
By printing the Watchdog Control and Status Register (CS) in the SCU board_init() I get the value:
WDOG_SC->CS = 0x25E2
That means WDOG is enabled with interrupts, clock source is LPO_clk, configuration successfull, locked.
However, if I print several times with delays the WD Counter Register (WDOG_SC->CNT), the value is always 0x0, like if the clock it is not running. This configuration, which is the default one as in WDOG32_GetDefaultConfig(), can be applied with success to the WDOG of the Cortex-M4 0. In this case everything runs as expected, the LPO clock correctly increments the CNT register. (The only weird thing is that the Reference Manual states that the CM40 is enabled by default, which is not true: it has to be enabled explicitly).
If I reconfigure the SCU WDOG to use the Internal Clock instead of the LPO one, the CNT register runs and the WDOG triggers.
However, no one will refresh the SCU WDOG, and the SCU gets rebooted.
- The SCU lpo_clk seems not working, while Cortex-M4-0 lpo_clk works. Is that expected?
- Is it true that the SCU WDOG is automatically started after a reset? (That's not true for C-M4-0)
- Who kicks the SCU WDOG and at which frequency? That's in the prebuilt SCU part?
Tested SCU versions: 1.2.x, 1.5.0 (with the same outcome)