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DDR DRAM mode register address bits

Question asked by Dallas Clow on Jun 28, 2020
Latest reply on Jun 29, 2020 by Dallas Clow

Are the bank address bits of the mode register settings (two msb's) of each field in DDR_SDRAM_MODE and DDR_SDRAM_MODE_2 used by the DDR controller at initialization or are they ignored?  There is a separate field for each specific mode register, which should allow the bank address bits to be ignored when addressing the DRAMs.  We're trying to assess the impact of a SW bug that incorrectly set the two msb's of the ESDMODE, ESDMODE2, and ESDMODE3 fields.  Would these to bits be ignored or cause incorrect DRAM mode register writes?