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ODT and additive latency

Question asked by Dallas Clow on Jun 28, 2020
Latest reply on Jun 29, 2020 by Bulat Karymov

The ODT_WR_CFG parameter of the CSn_CONFIG register indicates that write latency plus additive latency must be at least 3 to use ODT.  Our application uses an MPC8610 with 64-bit DDR2 w/ECC running at 200 MHz (DDR400).  Nominal CAS Latency is 3 and write latency is 2.  ODT is required.  Can CAS latency of 3, write latency of 2, and additive latency of 1 be used to meet this requirement and utilize ODT?  If so, should the RD_TO_PRE field of the TIMING_CFG_2 register include the additive latency (1 additional clock) or should it just include the t_RTP duration (2 clocks) when additive latency is used?

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