What are the P2020 input clock specifications when taking oscillator tolerance into account?
1) System clock: Max spec is 100MHz. If using a 100MHz oscillator with +/-100ppm drift, does that violate the max limit?
2) DDR input clock: Min spec is 66.7MHz. If using a 66.67MHz oscillator with +/-100ppm drift, does that violate the max limit?
3) SGMII clock: SGMII transmit and receiver Unit Interval spec is 800ps +/-100pm. Does this mean the SGMII input clock must be within +/- 100ppm?