I am using all 4 SPI busses on the Chip, and found the following. If I use an SPI with DMA in master mode I have no issues with it and it is working all the time. If I use an SPI in master mode with interrupts I found that if there is another SPI also using interrupts on a different bus transmitting at the same time the SPI set with the lower interrupt priority falls over. The received data on that SPI received by another device have CRC errors, and the data is not received all the time. The reason for using an SPI with interrupts is that it takes too much time to set up the particular SPI with DMA, I can not do this automatically with DMA via periodic triggering as the buffer and buffer size it transmits from varies all the time and is dependent on other things in the software. If I change the interrupt priorities around, the SPI with the highest interrupt priority always works, and the one with the lower priority always fails. I then shortened the message length and increased the clocking rate of 1 SPI to ensure that the transmit time of 2 SPI's on different busses using interrupts never overlap. So in other words when I start another SPI transfer on a different SPI bus with interrupts, there is no SPI that is configured with interrupts transmitting at that time. This solved my problem, but I would like to confirm if this is the case? If you want to have more than 1 SPI transmissions active at the same time at least 1 of them must be configured to use DMA? If you want to transmit 3 SPI transmissions on 3 different SPI busses at the same time at least 2 of them must be configured with DMA? Can you please confirm if my conclusion is correct?