MPC5675K ADC DMA bus error

tomtasjohan · ‎06-22-2020

Hi all,

I seem to be missing something in my attempt to read ADC data with DMA.

The code below results in a DMAES[SBE] (Source Bus Error). When I set SADDR to a local SRAM variable it works fine. The ADC works fine, i.e. I can read out ADC_0.CDR[0].R with expected data from CPU. This would lead me to believe that the MMU is correctly configured. PBRIDGE is untouched from reset conditions and the MPU is disabled.

I've tried with different SSIZEs but it does not help.

Any ideas?!

Kind regards,
Johan

    EDMA_0.DMACR.B.ERGA = 1; // Enable Round-robin Group Arbitration
    EDMA_0.DMACR.B.ERCA = 1; // Enable Round-robin Channel Arbitration

    EDMA_0.DMACR.B.EMLM = 1; // Enable minor loop offset
    EDMA_0.DMACR.B.EMLM = 0; // Disable minor loop offset

    EDMA_0.TCD[4].SADDR = (uint32_t) &ADC_0.CDR[0].R; // 0xFFE00100

    EDMA_0.TCD[4].SMOD = 0;
    EDMA_0.TCD[4].SOFF = 0; // Jump 0 bytes every minor
    EDMA_0.TCD[4].SSIZE = 2; // 32 bit

    EDMA_0.TCD[4].DOFF = 4; // Jump 4 bytes every minor
    EDMA_0.TCD[4].DSIZE = 2; // 32 bit
    EDMA_0.TCD[4].DMOD = 0;

    EDMA_0.TCD[4].CITERE_LINK = 0;
    EDMA_0.TCD[4].BITERE_LINK = 0;
    EDMA_0.TCD[4].BWC = 0; // 3
    EDMA_0.TCD[4].MAJORLINKCH = 0;
    EDMA_0.TCD[4].DONE = 0;
    EDMA_0.TCD[4].ACTIVE = 0;
    EDMA_0.TCD[4].MAJORE_LINK = 0;
    EDMA_0.TCD[4].E_SG = 0;
    EDMA_0.TCD[4].D_REQ = 0;
    EDMA_0.TCD[4].INT_HALF = 0;
    EDMA_0.TCD[4].INT_MAJ = 0;
    EDMA_0.TCD[4].START = 0;

    // Number of bytes to be transferred in each service request of the channel
    EDMA_0.TCD[4].NBYTES = 4;
    
    // TCD Last Source Address Adjustment
    EDMA_0.TCD[4].SLAST = 0; //-1*4;

    // TCD Destination Address
    EDMA_0.TCD[4].DADDR = (uint32_t) adc0_dma;  //Destination Address
    
    // Major Loop Count
    EDMA_0.TCD[4].BITER = EDMA_0.TCD[4].CITER = 1;

    // TCD Last Destination Address Adjustment/Scatter Gather Address
    EDMA_0.TCD[4].DLAST_SGA = -1*4;

    // Enable ADC channels for DMA transfer
    ADC_0.DMAE.B.DMAEN = 1;
    ADC_0.DMAR0.R = 1;

    EDMA_0.DMAERQL.B.ERQ04 = 1; // Enable channel 4
    
    DMAMUX_0.CHCONFIG[4].R = 0x80 | 20;
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tomtasjohan · ‎06-22-2020

Figured out the missing link, proper master/peripheral access needed to be set up in PBRIDGE_0. Case closed!

// eDMA master
PBRIDGE_0.MPROT0_7.B.MPROT2_MTR = 1;
PBRIDGE_0.MPROT0_7.B.MPROT2_MTW = 1;
PBRIDGE_0.MPROT0_7.B.MPROT2_MPL = 1;‍‍‍‍