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clock configuration for SPE PHY and RT1064

Question asked by frankk on Jun 18, 2020
Latest reply on Jun 22, 2020 by jeremyzhou



I would like to connect a single pair ethernet PHY (RMII) to RT1064. There are two modes for the PHY, master and slave mode.

In slave mode the PHY receives a 50MHz reference signal on its crystal input Xi pin. For this I would use ENET1_TX_CLK pin as 50MHz output clock derived from ref_enetpll. I think this is clear.

In PHY master mode the PHY outputs a 50MHz reference clock and it needs additonally a 25MHz crystal clock on its Xi pin. For this I would connect the 50MHz PHY reference clock to ENET1_REF_CLK. And to save the crystal I would leave the ENET1_TX_CLK connection to Xi pin of the PHY.


In that point I would say the RT1064 reference manual is not precise. Is it possible to use input ENET1_REF_CLK as the module reference clock and simultaneously a 25MHz ENET1_TX_CLK derived from ref_enetpll?


Any advice would be appreciated.