i.MX6 Dual Lite DRAM_SDCLK0/1 questions

[m_c]

1. In ref design SCH, 4 DDR chips and 64 bit DDR bus is used. But customer just use 2 DDR chips with 32bit bus, Does customer need to use CLK0 or CLK1? Or CLK0 for one DDR chip and the other use CLK1?

2. If customer just use only one CLK, still need to terminate the other one CLK with resistor?

3. If customer use T technology routing, still need to use these terminators? Where to put the resistor in layout? Close to which DDR?

[Yuri · Accepted solution]

Hello,

  Customers can use any DRAM clock:   https://community.nxp.com/message/1239257 

For signals termination - it makes sense to perform simulation to find most
suitable solution.

Regards,

Yuri.